Contention-Aware Dynamic Memory Bandwidth Isolation with Predictability in COTS Multicores: An Avionics Case Study

Over the past years, multicore systems emerged into the domain of hard real-time systems. Thesesystems introduce common buses and shared memories which heavily influence the timing behav-ior. We show that existing WCET optimizations may lead to suboptimal results when appliedto multicore setups. Additionally we provide both a genetic and a precise Integer Linear Pro-gramming (ILP)-based static instruction scratchpad memory allocation optimization which arecapable of exploiting multicore properties, resulting in a WCET reduction of 26% in averagecompared with a bus-unaware optimization. Furthermore, we show that our ILP-based optimiza-tion’s average runtime is distinctively lower in comparison to the genetic approach. Althoughlimiting the number of tasks per core to one and partially exploiting private instruction SPMs, wecover the most crucial elements of a multicore setup: the interconnection and shared resources. 1998 ACM Subject Classification C.3 Special-Purpose and Application-Based Systems,D.3.4 Processors, G.1.6 Optimization